A novel single switch-capacitor DAC SAR ADC design(MS)

Show simple item record

dc.contributor.advisor Dr. Sanjeev Manhas
dc.contributor.author Joshi, Ashish S
dc.date.accessioned 2020-06-29T06:28:46Z
dc.date.available 2020-06-29T06:28:46Z
dc.date.issued 2014-07-21
dc.identifier.uri http://hdl.handle.net/123456789/225
dc.description A thesis submitted for the award of the degree of Master of Science under the guidance of Dr. Sanjeev Manhas (Faculty, SCEE) en_US
dc.description.abstract display designs (IVD and VR) and two variations in the type of interface-based training (manned and unmanned). A total of 60 subjects participated in the experiment, where 30 subjects were randomly assigned to simulations in IVD and the rest in VR. In both the simulations, 15 randomly selected subjects executed the manned interface first and the remaining 15 executed the unmanned interface first. Results revealed that participants performed better in VR compared to IVD design, and performed better when they executed the task in the unmanned interface first. In the third experiment, we investigated human performance in VR under varying degrees of task difficulty in a complex search-and-shoot simulation. Thirty healthy subjects played both the novice and professional scenarios in the VR design. Half of the participants were given novice training first, and half of the participants were given professional training first. In this experiment, we investigated the effect of novice training on transfer and the effect of professional training on transfer. We took various cognitive and behavioral measures into consideration for statistical analyses. Results disclosed that the participants who faced the professional scenario first fared better at transfer to the novice scenario than the participants who faced the novice scenario first. We highlight the implications of our results for training personnel in indirect visual displays and virtual reality systems under varying target-distractor base-rates, manned-unmanned training and difficulty training. Maximum drive is obtained while employing shorted gate (SG) FinFET design for regulated clocked current mirror, sampling unit and SAR control circuitry. The option to separately bias the two gates of FinFE Tand operate the minde pen dently isutilized in comparator design to reduce the power dissipation at higher conversion speed. When compared to 90 nm CMOS ADC, this FinFET based ADC consumes only 2.25 µW of additional power and achieves nine times higher sampling rate.
dc.language.iso en_US en_US
dc.publisher IITMandi en_US
dc.subject ADC Circuit en_US
dc.subject SAR en_US
dc.title A novel single switch-capacitor DAC SAR ADC design(MS) en_US
dc.type Thesis en_US


Files in this item

This item appears in the following Collection(s)

Show simple item record

Search IIT Mandi Repository


Advanced Search

Browse

My Account