Desing and analysis of front-end electronics for CMOS pixel detectors (PhD)

Abstract

With the development in semiconductor industry, silicon pixel detectors have become an important class of sensing devices for imaging applications. In the present era, these detectors cover a broad spectrum of applications viz. photo cameras, bio-medical imaging, X-ray astronomy, space science, radar imaging, and automotive industry. Modern day semiconductor technologies can offer peculiar features to ameliorate the functionality of such systems provided that the foundries allow modifications in the process. High-voltage highresistive (HV-HR) multi-well process is one of the examples which may benefit the charge collection properties and fill factor percentage. Generally, achieving 100 % fill factor while hosting the signal processing circuitry in a sensor diode, may lead to having noise in terms of fluctuations at the-n-well substrate of pMOS transistors. Moreover, the coupling between the pixels via interpixel capacitances introduces crosstalk and may influence the signal charge of the pixel. Therefore, this thesis presents theory, design, implementation, and analysis of a pixel detector with 100 % fill factor. For this, the triple-well STMicroelectronics’ BCD8 160 nm technology is used first time as a chosen process foundry to demonstrate the concept and validation of the analysis. The signal processing circuitry consists of a charge sensitive amplifier (CSA), a shaper and a comparator with a cross-corner PVT independent threshold tuning circuit. In this chain of blocks, the CSA is a principal block that defines the performance of the analog front-end. The design of the CSA might be prone to fabrication processvariations. Hence,anon-chip corner control circuit is proposed and implemented to obtain the process independent functionality. The interpixel crosstalk becomes significant due to small distance between the pixels in modern detector arrays. The performance of the pixel detectors is also affected by its presence along with the electronic noise. The design process can be optimised and expedited if the noise and crosstalk models for these effects are available. Therefore, the analytical expressions for noise and crosstalk voltages in the analog front-end of pixel detectors are focussed in this research work. Firstly, the noise and crosstalk models are developed for the front-end which has a conventional CSA architecture. Nevertheless, it is observed that the conventional CSA has a limitation with respect to noise. The zero-pole modulation-demodulation with a pulsed reset mechanism is a technique for noise reduction in low rate applications. On the contrary, a continuous reset feedback network is a viable solution for high rate applications. In this work, the continuous reset zero-pole transformation CSA (ZPT-CSA) has been analysed and a complete transfer function is derived for this CSA. A comparative study is carried out to support the effectiveness of the continuous reset ZPT-CSA over the conventional CSA, in noise reduction. The noise models are also developed for the front-end with the continuous reset ZPT-CSA architecture. The measurement results and circuit simulations are demonstrated to verify the noise and crosstalk models of front-ends with the conventional and the ZPT-CSA, respectively. The designed chip with the conventional CSA architecture is taped-out and characterised using the transient and the noise measurement results. The comparison of noise models with their respective measurement and simulation results show good agreement with each other. Therefore, these noise models can be used for an efficient pixel detector design for the required noise specifications.