Multivalent energy-efficient CMOS amplifier and data converters for signal processing application (PhD)

Abstract

The advancement of technology has ushered a higher demand for wireless, portable and wearable internet-of-things devices in health monitoring, medical imaging, environmental sensing, communication, agricultural and several other industrial sectors. Analog signal processing (ASP) is an important aspect of various integrated systems that are required in these applications. Miniaturized technology for system design, power dissipation, noise performance, and area consumption are identified as the major challenges for implementing an ASP system. This thesis work addresses the performance-limiting design trade-offs in the amplifier and analog-to-digital converter (ADC) components of the ASP by concentrating on the analysis, design, and implementation of multivalent and configurable circuit techniques that can ameliorate area, noise, and energy efficiencies of the ASP systems. A low noise chopper amplifier with discrete time parametric amplifier (DTPA) as the signal demodulator is demonstrated using the chip taped-out in a standard 180 nm CMOS technology. The DTPA demodulator enables 8 dB gain enhancement during down-conversion of the chopped signal with out compromising on the input impedance and are a of the capacitively coupled amplifier in low-frequency data acquisition. Simultaneous concerns between power consumption, unity-gain bandwidth(UGBW) and settling accuracyof an operational transconductance amplifier (OTA) used for medical imaging applications are also addressed herein. A methodology to improve the UGBW and phase margin of a high-speed gain boosted OTA with a positive feedback capacitor across the auxiliary op-amp is presented, and 17% improvement in 0.01% settling time is demonstrated based on the presented symbolic analysis. Moreover,a reduced switching activity mode for a successive approximation register (SAR) ADC is developed to minimize power dissipation in the case of multi-sensory applications. Elimination of dispensable switching activity using a temporal reference and maximum design simplicity imposed on the ADC architecture provide easy configurability for the low frequency operation. A secondary switch-and-compare method to generate a supplementary least significant bit is described as well. The technique improves the figure-of-merit of the proof-of-concept SAR ADC with minimal power and area overhead.