Alternate high-k dielectrics for next -generation CMOS logic and memory technology (PhD)

Abstract

Incessant scaling of electronic devices in integrated circuits (ICs), since 50 years in accordance with celebrated Moore’s Law has revolutionized the semiconductor industry and become an integral part of our day to day life. It has been dictating the exponential growth of chip complexity with decreasing device feature size, and concurrent improvements in circuit speed, memory capacity, and cost per bit. Currently, it is commonly cited that transistors scaling is approaching nano-metric regime and hitting with many fundamental device physics and technology roadblocks. To maintain the higher performance and functionality of scaled logic and memory devices at lower power consumption and affordable costs as required for next generation technology node, the dielectric materials have decreased in thickness from hundreds of nanometers (nm) to atomistic boundaries. This gives rise to a number of fundamental device physics concerns such as increase in leakage current, power dissipation, channel mobility degradation, decrease in reliability and lifetime for logic and memories devices, as well as process challenges that include integration and optimization of new materials in current semiconductor processing. Moreover, these issues are not only about the inability of the scaled device performance and reliable operation but also the constraints from the material scientists, economist and technologist point of view. Thus, numerous attempts are being made to introduce new alternate dielectric materials and device structure, especially for logic and memory applications, so that the transistor scaling is not hampered in near future. High-κ dielectrics have emerged as a promising solution for next generation logic and memory applications. Therefore, in this work, the performance, reliability and lifetime of alternate high- dielectric materials are methodically investigated by non-destructive, nanoscopic and microscopic techniques for CMOS logic, embedded read only memory and ferroelectric non-volatile memory applications. For logic devices, erbium oxide (Er2O3) shows reasonable dielectric constant, lower leakage current density, higher conduction band offset and Gibbs free energy in contact with silicon, therefore has attracted wide attention of the scientific community. Thus, Er2O3 MOS capacitors are fabricated with variation in post-deposition annealing treatment and characterized with various physical, optical and electrical techniques. It reveals that the post deposition furnace annealing (FA) treatment is suitable to obtain high-quality high- erbium oxide thin films on active silicon with negligible interfacial oxide formation, low leakage current density, and insignificant hysteresis as desired for CMOS logic applications. The charge trapping and decay analysis of erbium oxide ultrathin films on silicon are systematically investigated by nanoscopic Kelvin probe force microscopy (KPFM) technique and Er2O3 MOS capacitors by microscopic capacitance-voltage (C-V) technique. A simple method is proposed and investigated for trap density estimation using nanoscopic KPFM technique and compared with the conventional macroscopic C-V measurements based trap density estimation method. Moreover, the continuing advancement in semiconductor technology increasingly requires a significant amount of reliable embedded memory to be integrated with other logic devices circuitry, to take the benefit of on-chip interconnects, higher data rate and also the realization of high-performance futuristic system on chip (SOC) technology. For on-chip embedded memories, bilayer gate stacks have the potential to continue scaling of flash memories to sub-20 nm nodes for short-term by reducing the gate stack thickness and minimize the fundamental cross-coupling capacitance issues among adjacent cells, but the charge trapping mechanism is not well understood and also not well-established, till date. For embedded memories, Al2O3 has attracted wide attention because of moderate dielectric constant, high band gap, low-leakage current, high thermal & kinetic stability, few bulk electrically active defects and availability of high-quality thin films formation with atomic layer deposition (ALD) processing. Since SiO2 layer has the minimum defects, and excellent interface with Si, so direct investigation of charge trapping in high-quality Al2O3 or Al2O3/SiO2 interface can be investigated, especially for embedded memory applications. Thus, Al/Al2O3/SiO2/Si, MAOS capacitors are fabricated by atomic layer deposition (ALD) and plasma enhanced chemical vapour deposition (PECVD) based Al2O3 and SiO2 thin films, respectively. The fabricated MAOS devices showed high memory window, low leakage current density and high breakdown field that proved the fabricated MAOS structures suitable for on-chip multi-level read only memory applications. The charge trapping properties i.e. trap centroid, trap density and lifetime of bi-layer Al2O3/SiO2 gate stack on Si are investigated by nanoscopic KPFM technique and MAOS capacitors by microscopic techniques. Further, the trap density is estimated systematically by the proposed technique using KPFM at room temperature and compared to the conventional constant current stress based trap density estimation method. Thus, because of high memory window at high voltage the Al/Al2O3/SiO2/Si, MAOS system is suitable for high voltage electrically erasable read only type embedded memory applications for bios/code storage. In the near future to meet the increasing demand of memory density, as a long-term solution, an alternate, and reliable storage mechanism is required, i.e. non-charge storage based emerging memories, because further scaling of charge stored based memories is hampered by the fewer number of stored electrons that lead to threshold voltage instability due to statistical fluctuations. In this regard, for storage class memories, High-κ metal-ferroelectric-insulator-semiconductor (MFIS) structure of ferroelectric memories is a prospective contender due to its fast access time, low power consumption, radiation tolerance, non-destructive readout, excellent retention, and endurance time. Among the ferroelectric materials, PbZrTiO3 (PZT) showed high dielectric constant, high remanent polarization, low crystallization temperature and good thermal stability. Also, the titanium oxynitride (TiOxNy) has shown exceptional physical and chemical properties, such as high dielectric constant, higher resistance to interfacial oxide formation, and an excellent diffusion barrier. Thus, TiOxNy buffer layer is expected as an exceptional candidate for non-volatile ferroelectric memory applications. Therefore, Au/PZT/TiOxNy/Si, MFIS capacitors are fabricated using TiOxNy buffer and PZT ferroelectric thin films on p-Si by RFmagnetron sputtering and annealed in N2 ambient. The material characteristics of deposited thin films are investigated by XRD, Micro Raman and AFM analysis that revealed the desired TiOxNy rutile, PZT perovskite phases, and high-quality uniform multi-layer interfaces, respectively. Further, the electrical characteristics of Au/PZT/TiOxNy/Si, MFIS structures revealed the large memory window, low leakage current, high breakdown strength and exceptional data retention. Moreover, the fabricated devices showed good memory characteristics when subjected to thermal and constant voltage stress that proved the reliability of TiOxNy buffer layer for ferroelectric field effect transistor applications.